Intel BX80605I7870 - Core i7 2.93 GHz Processor Manual, Datasheet

Manual, Datasheet for Intel BX80605I7870 - Core i7 2.93 GHz Processor Processor (98 pages)

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474/474291-bx80605i7870__core_i7_293_ghz_processor.pdf file (15 Oct 2023)
  • Manufacturer: Intel
  • Category of Device: Processor
  • Document: BX80605I7870 - Core i7 2.93 GHz Processor, File Type: PDF Datasheet
  • Updated: 15-10-2023
  • Count of Pages: 98
Download BX80605I7870 - Core i7 2.93 GHz Processor Manual (98 pages)

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Data: UPD 15th October 2023

Intel BX80605I7870 - Core i7 2.93 GHz Processor Processor PDF Datasheet (Updated: Sunday 15th of October 2023 07:32:10 AM)

Rating: 4.2 (rated by 44 users)

Compatible devices: Atom N270, XScale Core, I5 3570K, CORE 2 DUO MOBILE - THERMAL DESIGN GUIDE 6-2008, Pentium II Xeon, 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - THERMAL MECHANICAL S AND DESIGN GUIDELINES 01-2011, 80386, IXP2400.

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Text Version of Intel BX80605I7870 - Core i7 2.93 GHz Processor Processor Manual (Summary of Contents)

(Ocr-Read of Intel BX80605I7870 - Core i7 2.93 GHz Processor Document (Main Content), UPD: 15 October 2023)

  • 45, Datasheet 45 Register Description 2.6.5 SAD_PCIEXBAR Global register for PCIEXBAR address space. 2.6.6 SAD_DRAM_RULE_0, SAD_DRAM_RULE_1, SAD_DRAM_RULE_2, SAD_DRAM_RULE_3 SAD_DRAM_RULE_4, SAD_DRAM_RULE_5 SAD_DRAM_RULE_6, SAD_DRAM_RULE_7 This register provides SAD DRAM rules. Address Map for p…

  • 5, Datasheet 5 2.10.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD.........................................74 2.10.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_2_ODT_MATRIX_RANK_…

  • 6, 6 Datasheet 2.10.39 Error Injection Implementation ...............................................................84 2.11 Integrated Memory Controller Channel Address Registers........................................85 2.11.1 MC_DOD_CH0_0, MC_DOD_CH0_1, MC_DOD_CH0_2 ..................…

  • 94, Intel BX80605I7870 - Core i7 2.93 GHz Processor Register Description 94 Datasheet 2.13.5 MC_THERMAL_PARAMS_B0 MC_THERMAL_PARAMS_B1 MC_THERMAL_PARAMS_B2 Parameters used by the thermal throttling logic. 2.13.6 MC_COOLING_COEF0 MC_COOLING_COEF1 MC_COOLING_COEF2 Heat removed from DRAM 8 DCLKs. This should be scaled relative to the per command …

  • 63, Datasheet 63 Register Description 2.10.5 MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD MC_CHANNEL_2_DDR3CMD DDR3 Configuration Command. This register is used to issue commands to the DIMMs such as MRS commands. The register is used by setting one of the *_VALID bits along with the appropri…

  • 71, Datasheet 71 Register Description 2.10.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING MC_CHANNEL_2_CKE_TIMING This register contains parameters that specify the CKE timings. All units are in DCLK. 2.10.15 MC_CHANNEL_0_ZQ_TIMING MC_CHANNEL_1_ZQ_TIMING MC_CHANNEL_2_ZQ_TIMING Th…

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