Cypress Semiconductor CY7C1310BV18 Manual, Specification Sheet

3, CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 3 of 29 Logic Block Diagram (CY7C1312BV18) Logic Block Diagram (CY7C1314BV18) 512K x 18 Array CLK A (18:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. RPS WPS Control Log…

19, CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 19 of 29 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either HIG…

27, CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 27 of 29 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25MCAB Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PL…

28, Cypress Semiconductor CY7C1310BV18 CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 28 of 29 Document History Page Document Title: CY7C1310BV18/CY7C1910BV18/CY7C1312BV18/CY7C1314BV18, 18-Mbit QDR™-II SRAM 2-Word Burst Architecture Document Number: 38-05619 Rev. ECN No. Submission Date …

18, CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 18 of 29 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 26N 299G 566A 831J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 57R 329F …

11, CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 11 of 29 Write Cycle Descriptions The write cycle description table for CY7C1910BV18 follows. [2, 8] BWS 0 K K Comments L L–H – During the data portion of a write sequence, the single byte (D [8:0] ) is…